The QSFP-40G-LR4 is a transceiver module designed for 10Km optical communication applications. The design is compliant to 40GBASE-LR4 of the IEEE P802.3ba standard. The module converts 4 inputs channels (ch) of 10Gb/s electrical data to 4 CWDM optical signals, and multiplexes them into a single channel for 40Gb/s optical transmission. Reversely, on the receiver side, the module optically de-multiplexes a 40Gb/s input into 4 CWDM channels signals, and converts them to 4 channel output electrical data.
40G QSFP LR4 Fiber Optic Transceiver Features:
4 CWDM lanes MUX/DEMUX design
Up to 11.2Gbps per channel bandwidth
Aggregate bandwidth of > 40Gbps
Duplex LC connector
Compliant with 40G Ethernet IEEE802.3ba and 40GBASE-LR4 Standard
QSFP MSA compliant
Up to 10 km transmission
Compliant with QDR/DDR Infiniband data rates
Single +3.3V power supply operating
Temperature range 0°C to 70°C
RoHS Compliant Part
40G QSFP LR4 Fiber Optic Transceiver Applications:
Rack to rack
Data centers Switches and Routers
Metro networks
Switches and Routers
40G BASE-LR4 Ethernet Links
The central wavelengths of the QSFP-40G-LR4 4 CWDM channels are 1271, 1291, 1311 and 1331 nm as members of the CWDM wavelength grid defined in ITU-T G694.2. It contains a duplex LC connector for the optical interface and a 38-pin connector for the electrical interface. To minimize the optical dispersion in the long-haul system, single-mode fiber (SMF) has to be applied in this module.
The QSFP-40G-LR4 is designed with form factor, optical/electrical connection and digital diagnostic interface according to the QSFP Multi-Source Agreement (MSA). It has been designed to meet the harshest external operating conditions including temperature, humidity and EMI interference.
The QSFP-40G-LR4 operates from a single +3.3V power supply and LVCMOS/LVTTL global control signals such as Module Present, Reset, Interrupt and Low Power Mode are available with the modules. A 2-wire serial interface is available to send and receive more complex control signals and to obtain digital diagnostic information. Individual channels can be addressed and unused channels can be shut down for maximum design flexibility.
The QSFP-40G-LR4 is designed with form factor, optical/electrical connection and digital diagnostic interface according to the QSFP Multi-Source Agreement (MSA). It has been designed to meet the harshest external operating conditions including temperature, humidity and EMI interference. The huihongfiber 40G module offers very high functionality and feature integration, accessible via a two-wire serial interface.
- Absolute Maximum Ratings
| Parameter | Symbol | Min. | Typical | Max. | Unit |
| Storage Temperature | TS | -40 | +85 | °C | |
| Supply Voltage | VCCT, R | -0.5 | 4 | V | |
| Relative Humidity | RH | 0 | 85 | % |
- Recommended Operating Environment:
| Parameter | Symbol | Min. | Typical | Max. | Unit |
| Case operating Temperature | TC | 0 | +70 | °C | |
| Supply Voltage | VCCT, R | +3.13 | 3.3 | +3.47 | V |
| Supply Current | ICC | 1000 | mA | ||
| Power Dissipation | PD | 3.5 | W |
- Electrical Characteristics (TOP = 0 to 70 °C, VCC = 3.13 to 3.47 Volts
| Parameter | Symbol | Min | Typ | Max | Unit | Note |
| Data Rate per Channel | – | 10.3125 | 11.2 | Gbps | ||
| Power Consumption | – | 2.5 | 3.5 | W | ||
| Supply Current | Icc | 0.75 | 1.0 | A | ||
| Control I/O Voltage-High | VIH | 2.0 | Vcc | V | ||
| Control I/O Voltage-Low | VIL | 0 | 0.7 | V | ||
| Inter-Channel Skew | TSK | 150 | Ps | |||
| RESETL Duration | 10 | Us | ||||
| RESETL De-assert time | 100 | ms | ||||
| Power On Time | 100 | ms | ||||
| Transmitter | ||||||
| Single Ended Output Voltage Tolerance | 0.3 | 4 | V | 1 | ||
| Common mode Voltage Tolerance | 15 | mV | ||||
| Transmit Input Diff Voltage | VI | 150 | 1200 | mV | ||
| Transmit Input Diff Impedance | ZIN | 85 | 100 | 115 | ||
| Data Dependent Input Jitter | DDJ | 0.3 | UI | |||
| Receiver | ||||||
| Single Ended Output Voltage Tolerance | 0.3 | 4 | V | |||
| Rx Output Diff Voltage | Vo | 370 | 600 | 950 | mV | |
| Rx Output Rise and Fall Voltage | Tr/Tf | 35 | ps | 1 | ||
| Total Jitter | TJ | 0.3 | UI | |||
Note:
- 20～80%
- Optical Parameters(TOP = 0 to 70 °C, VCC = 3.0 to 3.6 Volts)
| Parameter | Symbol | Min | Typ | Max | Unit | Ref. |
| Transmitter | ||||||
| Wavelength Assignment | L0 | 1264.5 | 1271 | 1277.5 | nm | |
| L1 | 1284.5 | 1291 | 1297.5 | nm | ||
| L2 | 1304.5 | 1311 | 1317.5 | nm | ||
| L3 | 1324.5 | 1331 | 1337.5 | nm | ||
| Side-mode Suppression Ratio | SMSR | 30 | – | – | dB | |
| Total Average Launch Power | PT | – | – | 8.3 | dBm | |
| Average Launch Power, each Lane | -7 | – | 2.3 | dBm | ||
| Difference in Launch Power between any two Lanes (OMA) | – | – | 6.5 | dB | ||
| Optical Modulation Amplitude,each Lane | OMA | -4 | +3.5 | dBm | ||
| Launch Power in OMA minus | ||||||
| Transmitter and Dispersion Penalty(TDP), each Lane | -4.8 | – | dBm | |||
| TDP, each Lane | TDP | 2.3 | dB | |||
| Extinction Ratio | ER | 3.5 | – | – | dB | |
| Transmitter Eye Mask Definition {X1,X2, X3, Y1, Y2, Y3} | {0.25, 0.4,0.45,0.25,0.28, 0.4} | |||||
| Optical Return Loss Tolerance | – | – | 20 | dB | ||
| Average Launch Power OFF Transmitter, each Lane | Poff | -30 | dBm | |||
| Relative Intensity Noise | Rin | -128 | dB/HZ | 1 | ||
| Optical Return Loss Tolerance | – | – | 12 | dB | ||
| Receiver | ||||||
| Damage Threshold | THd | 3.3 | dBm | 1 | ||
| Average Power at Receiver Input, eachLane | R | -13.7 | 2.3 | dBm | ||
| Receiver Power (OMA), each Lane | 3.5 | dB | ||||
| Receive Electrical 3 dB upper Cut offFrequency, each Lane | 12.3 | GHz | ||||
| RSSI Accuracy | -2 | 2 | dB | |||
| Receiver Reflectance | Rrx | -26 | dB | |||
| Receiver Power (OMA), each Lane | – | – | 3.5 | dBm | ||
| Stressed Receiver Sensitivity inOMA, each Lane | – | – | -9.9 | dBm | ||
| Receiver Sensitivity, each Lane | SR | – | – | -11.5 | dBm | |
| Difference in Receive Power betweenany two Lanes (OMA) | 7.5 | dB | ||||
| Receive Electrical 3 dB upper CutoffFrequency, each Lane | 12.3 | GHz | ||||
| LOS De-Assert | LOSD | -15 | dBm | |||
| LOS Assert | LOSA | -30 | dBm | |||
| LOS Hysteresis | LOSH | 0.5 | dB | |||
Note: 12dB Reflection
- Timing for Soft Control and Status Functions
| Parameter | Symbol | Max | Unit | Conditions |
| Initialization Time | t_init | 2000 | ms | Time from power on1, hot plug or rising edge of Reset until the module is fully functional2 |
| Reset Init Assert Time | t_reset_init | 2 | μs | A Reset is generated by a low level longer than the minimum reset pulse time present on the ResetL pin. |
| Serial Bus Hardware Ready Time | t_serial | 2000 | ms | Time from power on1 until module responds to data transmission over the 2-wire serial bus |
| Monitor Data ReadyTime | t_data | 2000 | ms | Time from power on1 to data not ready, bit 0 of Byte 2, deasserted and IntL asserted |
| Reset Assert Time | t_reset | 2000 | ms | Time from rising edge on the ResetL pin until the module is fully functional2 |
| LPMode Assert Time | ton_LPMode | 100 | μs | Time from assertion of LPMode (Vin:LPMode =Vih) until module power consumption enters lower Power Level |
| IntL Assert Time | ton_IntL | 200 | ms | Time from occurrence of condition triggering IntL until Vout:IntL = Vol |
| IntL Deassert Time | toff_IntL | 500 | μs | toff_IntL 500 μs Time from clear on read3 operation of associated flag until Vout:IntL = Voh. This includes deassert times for Rx LOS, Tx Fault and other flag bits. |
| Rx LOS Assert Time | ton_los | 100 | ms | Time from Rx LOS state to Rx LOS bit set and IntL asserted |
| Flag Assert Time | ton_flag | 200 | ms | Time from occurrence of condition triggering flag to associated flag bit set and IntL asserted |
| Mask Assert Time | ton_mask | 100 | ms | Time from mask bit set4 until associated IntL assertion is inhibited |
| Mask De-assert Time | toff_mask | 100 | ms | Time from mask bit cleared4 until associated IntlL operation resumes |
| ModSelL Assert Time | ton_ModSelL | 100 | μs | Time from assertion of ModSelL until module responds to data transmission over the 2-wire serial bus |
| ModSelL Deassert Time | toff_ModSelL | 100 | μs | Time from deassertion of ModSelL until the module does not respond to data transmission over the 2-wire serial bus |
| Power_over-ride orPower-set Assert Time | ton_Pdown | 100 | ms | Time from P_Down bit set 4 until module power consumption enters lower Power Level |
| Power_over-ride or Power-set De-assert Time | toff_Pdown | 300 | ms | Time from P_Down bit cleared4 until the module is fully functional3 |
Note：
- Power on is defined as the instant when supply voltages reach and remain at or above the minimum specified value.
- Fully functional is defined as IntL asserted due to data not ready bit, bit 0 byte 2 de-asserted.
- Measured from falling clock edge after stop bit of read transaction.
- Measured from falling clock edge after stop bit of write transaction.